fed-l1c-iside-parity — Processor / logic board
The hardware error handler of the “Firestorm” performance cores (A14 / M1 chips) detected a parity error in the level 1 instruction cache (L1C, I side): data read from the cache no longer matched its check bit. This is an error detected by the processor hardware, not an app bug. The exact same string (@AppleFireStormErrorHandler.cpp:599) appears on an M1 MacBook Air, with different apps at the time of the crash; REWA classifies “fed err (parity…)” under NAND / SoC. An isolated case may be a transient error; repeats point to the SoC or its power supply on the logic board.
iPhone
SoC / logic board (parity error in a performance core's L1 instruction cache)
Low confidenceVerified sourceProcessor / logic board
First check
Count the occurrences: a single log → update iPadOS and monitor.
Sources
- Mac-Forums – MacBook Air M1: “FED err (L1C I-side data parity) on P-core” @AppleFireStormErrorHandler.cpp:599 ↗
- REWA – iPhone restart log analysis (fed err parity → NAND, SoC) ↗
- Eclectic Light – M1 boot: AppleFireStormErrorHandler (ARM64 error handler) ↗
- Apple XNU – sleh.c (is_parity_error → panic “Kernel parity error”) ↗